Photolithography is a common technique employed in the manufacture of semiconductor devices. Typically, a semiconductor wafer is coated with a layer (film) of light-sensitive material, such as photoresist. Using a patterned mask or reticle, the wafer is exposed to projected light, typically actinic light, which manifests a photochemical effect on the photoresist, which is subsequently chemically etched, leaving a pattern of photoresist "lines" on the wafer corresponding to the pattern on the mask.
This is all good in theory, until one acknowledges that the uniformity of the illuminating light varies, typically at the source of the light, and that such non-uniformity will manifest itself in the size of features (e.g., photoresist lines) that can be created on the wafer. To the end of uniformizing the light incident on and passing through the mask, various techniques have been proposed, among these a technique discussed in commonly-owned U.S. Pat. No. 5,055,871 (Pasch).
The ultimate goal of uniformizing (homogenizing) the incident light is that the illumination uniformity (i.e., non-uniformity) of photolithographic apparatus will often set a limit to how small a feature, such as a line, can be imaged in a manufacturing environment. And, as a general principle, being able to create smaller integrated circuit features is better (faster, more compact, etc.).
Of no less concern than the ultimate size (smallness) of features, is the ability to control the critical dimension ("cd") from one feature to another. For example, since size generally equates with speed (e.g., smaller is generally faster), it is disadvantageous to have one polysilicon ("poly") gate turn out smaller (and faster) than another poly gate on the same device. Conversely, it is highly desirable to fabricate all similar features (e.g., poly gates) to be the same size (i.e., with the same "cd"), especially in gate-array type devices.
Among the causes for this concern over "cd" are problems in the thickness of films overlying an irregular topography on the wafer surface. Prior to the numerous steps involved in fabricating integrated circuit devices on a semiconductor wafer, the wafer is initially fairly flat--exhibiting a relatively regular topography.
However, prior structure formation often leaves the top surface topography of the silicon wafer highly irregular, with bumps, areas of unequal elevation, troughs, trenches and/or other surface irregularities. As a result of these irregularities, deposition of subsequent layers of materials could easily result in incomplete coverage, breaks in the deposited material, voids, etc., if it were deposited directly over the aforementioned highly irregular surfaces. If the irregularities are not alleviated at each major processing step, the top surface topography of the surface irregularities will tend to become even more irregular, causing further problems as layers stack up in further processing of the semiconductor structure.
As mentioned above, the application and patterning of photoresist is typically a key step in the fabrication of complex integrated circuit devices, an is a procedure that may be repeated at several different times throughout the fabrication process.
It has been noticed, and is generally known, that the thickness of a subsequently applied film, particularly photoresist, will vary (in a generally non-predictable manner) depending upon the irregular topography of the underlying surface. (Application of an overlying film to a flat, regular surface is generally not a problem.) For example, a photoresist layer, even if spun-on, will exhibit a different thickness, from point-to-point over the wafer (and within the area of a given device) depending on the irregular topography of underlying features.
This variation in the thickness of photoresist over an irregular topography is graphically illustrated in FIG. 1A.
FIG. 1A shows a portion of a semiconductor wafer 110 which has been processed to develop raised structures 112a, 112b and 112c of Field Oxide (FOX), between which are active areas (islands) 114a and 114b having a lower elevation (e.g., at wafer level). The island 114a between the FOX structures 112a and 112b has a width w.sub.1 substantially smaller than the width w.sub.2 of the island 114b between the FOX structures 112b and 112c. Having islands of different widths is not uncommon. For example, the island 114a is an "array island" having a width w.sub.1 on the order of 3 microns, and the island 114b is "I/O (Input/Output) island" having a width w.sub.2 on the order of hundreds of microns. Both types of islands are usually required for an integrated circuit device, and it is not uncommon to have widely varying island sizes in a single device. In any case, the island areas are usually lower (less elevated) than the field oxide areas.
An overlying layer 120 of polysilicon ("poly") is deposited over the wafer, which already exhibits an irregular topography. This is according to known techniques, and is presented herein by way of example only.
An overlying film 130 of photoresist is applied, in any suitable manner, over the poly layer 120, and photolithographically treated to create etch-resistant "lines" (photochemically-converted areas) 132 and 134 over the active areas 114a and 114b, respectively. The line features 132 and 14 are shown in reverse cross-hatch from the remainder of the film 130.
Ultimately, the photoresist layer 130 is etched (or washed) away, leaving only a pattern of photochemically-converted areas 132 and 134 overlying the ploy 120. In subsequent fabrication steps, the wafer is etched (chemical, plasma, etc.), so that all but discrete poly regions 122 and 124 (shown in reverse cross-hatch) underlying respective photoresist features 132 and 134, respectively, are removed from the surface of the wafer. With additional processing, not shown, the poly regions 122 and 124 may perform at gates.
Since electron flow in the lateral direction (i.e., plane of the wafer) is of primary concern in the performance of circuit elements (e.g., poly gates), the transverse dimension of the poly gates 122 and 124 parallel to the plane of the wafer is of paramount interest. For purposes of this discussion, this transverse dimension is termed a "critical dimension", or "cd." The poly gate 122 has a first cd, designated "cd1", and the poly gate 124 has a second cd, different from the first cd, designated "cd2".
In essence, the cd's of the two poly gates are different, because the width of the respective overlying photoresist features is different. (Generally, the width of a poly gate will be essentially the same as that of the overlying resist feature.)
As mentioned above, it is nearly impossible to apply a uniform layer of photoresist over an irregular surface. Hence, the thickness of the photoresist 130 over the active area 114a (particularly over the area where the poly gate 122 is to be formed) is different than the thickness of the photoresist 130 over the active area 114b (particularly where the poly gate 124 is to be formed).
It is also generally known, that the reflectance of a film (such as photoresist) will vary with its thickness. However, since the thickness of an overlying film at any given point on the surface of the semiconductor wafer (e.g., photoresist) is not readily determinable, the reflectance is consequently indeterminate.
This indeterminate nature of resist thickness and reflectivity over irregular underlying surfaces has important, negative ramifications in the semiconductor fabrication process, especially in the process of fabricating circuit elements having "critical dimensions.
FIG. 1B illustrates the reflectivity problem, and its manifestation in the size of a photoresist feature. Here, in a photolithographic process, a film 140 of photoresist is exposed to light (arrows .dwnarw..dwnarw..dwnarw..dwnarw.) of hypothetically uniform intensity. A mask 150 is interposed in the light path, and is provided with light-transmitting areas (lines) 152 and 154 allowing light (.dwnarw..dwnarw.) to impinge upon selected areas 142 and 144, respectively, of the film 140.
In FIG. 1B, the thickness of the film 140 is intentionally shown to be different in the areas 142 and 144. And, as we will see, it is relatively insignificant that the film is thicker in the area 144 than in the area 142. And, we are ignoring, for purposes of this discussion, depth of field (depth of focus) issues that may arise from projecting a mask image onto a surface of varying height.
FIG. 1C illustrates graphically the effect of film thickness (horizontal axis) on reflectivity (i.e., the energy reflected by the film), and relates to the issues raised in FIG. 1B. While there is a general increase in reflectivity with increased thickness, there is a much more profound (generally sinusoidal) pattern of "maxima" 170a, 170b and 170c and "minima" 172a, 172b and 172c, which exhibits that the reflectivity for a given greater film thickness (point 172c) can well be less than the reflectivity for a given lesser film thickness (point 170b). (Dashed horizontal line 174 provided as a visual aid.) Importantly, these variations are dependent on relatively small, e.g., a quarter of a wavelength, variations in the thickness of the film--difficult dimensions to measure, let alone control.
Returning to FIG. 1B, it can be appreciated that it is rather indeterminate how much of the (supposedly uniform) incident energy (.dwnarw..dwnarw..dwnarw.) will be absorbed by the photoresist film, and how much will be reflected, at any given point. And, as a general proposition, the more incident energy (.dwnarw..dwnarw..dwnarw.) that is absorbed at a given point, the greater the area of the given feature 142 or 144 will "grow". Of course, the reverse would be true for reverse masking, wherein light acts outside of the desired feature, in which case the more light absorbed--the smaller the feature would be.)
In any case, the point is made that an irregular thickness of an overlying film (e.g., photoresist) will impact upon the ultimate dimension of underlying features (e.g., poly gate) being formed, with commensurate undesirable functional effects.
Certainly, if reflectivity issues were ignored, which they cannot be, the widths of all of the photoresist lines and underlying features would be well-controlled. However, because the photoresist thickness varies from point-to-point over the wafer, and consequently its reflectivity varies from point-to-point, the efficiency of the incident light on the photoresist layer will vary commensurately, which will affect the ultimate width of the resist features.
Evidently, the efficiency of the photolithography process is dependent on the ability of the photoresist material to absorb the radiant energy (light), and this ability is, in turn, affected by the thickness/reflectance of the photoresist.
In the prior art, it has been known to compensate approximately for known variations (and to some extend, gross trends can be predicted) in photoresist thicknesses by "differentially biasing" the line widths in the high versus low reflectivity areas. And FIG. 1C illustrates that, to some extent, one can reasonably assume that the average reflectivity for an area with greater film thickness will reflect more than an area of lesser thickness. This concept may be employed with respect to relatively large Input/Output (I/O) versus relatively small active areas.
And, as mentioned before, in the prior art, it has also been known to use "spin-on" or other techniques in an attempt to apply a film (e.g., photoresist) having a relatively planar top surface. Of course, a relatively planar top surface is of little help in uniformizing the thickness of a film over an underlying surface having an irregular topography--in which case the thickness of the film would vary widely from point-to-point.
It has also been known to reduce the viscosity of the photoresist so that it goes on in a more planar manner. But, thickness will vary according to the topography of the underlying surface. Further, changing the photoresist chemistry (viscosity) can have adverse side effects, such as poor photolithography resolution.
In the prior art, it has also been known to perform subsequent steps to planarize the photoresist, which can be somewhat effective in overcoming the reflectance issues set forth above--again, so long as the photoresist is planarized over a relatively planar underlying surface.
Prior art techniques for accommodating "cd" variations due to photoresist thickness variations are relatively difficult and time consuming to implement, and may not deliver the desired results.
The following patents, incorporated by reference herein, are cited of general interest: U.S. Pat. Nos. 4,977,330; 4,929,992; 4,912,022; 4,906,852; 4,762,396; 4,698,128; 4,672,023; 4,665,007; 4,541,169; 4,506,434; and 4,402,128.